Semiconductor nonvolatile memory with low programming voltage

ABSTRACT

A semiconductor nonvolatile memory cell comprised of a p-type silicon well  12,  an n +  drain  8  and an n +  source  10,  the source and the drain regions defining an channel region  7.  On top of the well  12  there are laminated a thin silicon dioxide film  2  served as a gate oxide, a polysilicon layer 32 and a SrTiO 3  layer  34  comprised of a high dielectric substance, in respective order. Further on top of these layers, there is formed a polysilicon layer  36 served as gate electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory device is constructed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor nonvolatile memory and, more particularly, to reduction of the applied programming voltage to write and erase information therein.

[0003] 2. Description of the Prior Art

[0004] Floating gate type memory is well known to be useful as the semiconductor nonvolatile memory (E²PROM). FIG. 1 schematically illustrates in section the construction of a prior art memory cell 1 of a floating gate type memory.

[0005] Referring to FIG. 1, there is formed a silicon substrate with a p-type silicon well 12 formed therein. A channel region 14 is formed from an n⁺ drain 8 and an n⁺ source 10 provided within the well 12. On top of the silicon well 12 there are formed a silicon dioxide film 2, a polysilicon layer 4 on top of film 2 and a silicon dioxide film 5 on top of layer 4. Further on top of film 5 there is formed a polysilicon control gate electrode 6. The silicon dioxide film 2 has a thin portion 2 a on top of drain 8 and the thickness of the portion 2 a is 10 nm.

[0006] Information can be written and erased into and from the memory cell 1 constructed as described above by electricity. The memory cell 1 has two stable information states: one in which a logic “0” has been written therein and the other in which the logic “0” has been erased and a logic “1” has been stored. The fact stable states is utilized for fabrication of a memory.

[0007] Operation of writing and erasing information into and from the memory cell 1 will be described below. To write a logic “0” into the memory cell 1, a high voltage which may be as much as approximately 20 voltage is applied to the drain 8 of the memory cell 1 relative to the gate electrode 6. As a result of application of this voltage, an electric field develops between the gate electrode 6 and the drain 8 which causes some of electrons within the polysilicon layer 4 to tunnel through the portion 2 a and enter the drain 8. This means that the memory cell 1 has the logic “0” written. The memory cell 1 with the logic “0” serves as a transistor with the lower threshold voltage. “Threshold voltage” is a gate voltage at which a current begins to flow between the source and the drain when the voltage applied to the gate electrode relative to the source is made to increase.

[0008] Meanwhile, to erase the logic “0” from the memory cell 1 and store the logic “1” therein, some of electrons within the drain 8 need injecting into the polysilicon layer 4. This is effected by generating an electric field of the opposite polarity to that produced when writing the logic “0” by applying a voltage of approximately 20 V to the gate electrode 6 relative to the drain 8 thereof. In this stable state in which the logic “0” is erase from the memory cell or the logic “1” is stored therein, the memory cell 1 serves as a transistor with the higher threshold voltage.

[0009] Next, the operation of reading information from the memory cell 1 will be described. It is decided whether a logic “0” is stored or a logic “1” is stored in each memory cell by determining whether or not current flows through the channel region 14 when a voltage of some 5 V is applied between the source 10 and the drain 8 of the memory cell 1 and no gate voltage is applied to gate 6.

[0010] More specifically, Since the memory cell 1 with a logic “0” behaves like a transistor with the lower threshold voltage as described above, and the applied gate voltage of 0 volts exceeds the lower threshold voltage there flows current through the channel region 14.

[0011] Meanwhile, when a logic “1” is stored in the memory cell 1, the memory cell 1 behaves like a transistor with the higher threshold voltage as described above, and the applied gate voltage of 0 volts does not exceed the higher threshold voltage. Thus no current flows through the channel region 14.

[0012] A semiconductor nonvolatile memory may be constructed by using memory cells such as described above coupled with read and write control transistor.

[0013] The above-mentioned nonvolatile semiconductor memory device has the following problem.

[0014] With progress of the semiconductor industry, the need for integrated nonvolatile semiconductor memories has arisen. The memories have had difficulties in further integration thereof. One of the difficulties is that the memory requires a highly insulated structure. That is because an applied programming voltage can destroy the device when the device does not have the highly insulated structure. Avoidance of the destruction is effected by reduction in applied programming voltage.

[0015] However, to write information into the memory, electrons need moving from the polysilicon layer 4 to the drain 8 through the silicon dioxide film portion 2 a. More specifically, a certain electric field strength or more has to be applied to the portion 2 a so that the electrons could tunnel through the portion 2 a. Meanwhile when the programming write voltage is applied to the gate of the memory cell 1 constructed as described above relative to the drain, the electric field strength applied to the portion 2 a is given by $\begin{matrix} {E = {\frac{{C1} + {C3}}{L \times \left( {{C1} + {C2} + {C3}} \right)}V_{s}}} & (1) \end{matrix}$

[0016] where C1, C2 and C3 are an electric capacity between the polysilicon layer 4 and the polysilicon layer 6, an electric capacity between the polysilicon layer 4 and the drain 8 and an electric capacity between the polysilicon layer 4 and the p-type well 12, respectively. L is the thickness of the porion 2 a of the silicon dioxide film.

[0017] Accordingly, when silicon dioxide is used as insulating layer, electric capacities C1, C2 and C3 are substantially same in the equation. Therefore, to make necessary electric field strength apply to the portion 2 a, a thinner silicon dioxide film portion 2 a has to be used or a high voltage which may be as much as 20 volts has to be applied to the gate 6. Because technology could limit the thinner silicon dioxide film portion 2 a the high voltage of approximately 20 volts is necessary to write information in the memory cell. That limits reduction in the programming write voltage.

SUMMARY OF THE INVENTION

[0018] Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device that allows information to be written therein at low voltage so that the miniaturization and integration of the nonvolatile semiconductor memory can be facilitated.

[0019] A nonvolatile memory according to an embodiment of the present invention, comprises:

[0020] a) a first conductive type semiconductor region;

[0021] b) a pair of second conductive type diffusion regions formed within said first conductive type semiconductor region forming source and drain diffusion regions separated by a channel region comprised of at least a portion of said first conductive type semiconductor region;

[0022] c) a first gate insulating layer formed on said first conductive type semiconductor region;

[0023] d) a floating gate conductive layer formed on said first gate insulating layer;

[0024] e) a second insulating layer formed on said floating gate conductive layer, said second insulating layer being comprised of a layer of insulating material which has a dielectric constant which is sufficiently high to lower a programming voltage needed to cause Fowler-Nordheim tunneling of charges into or out of said floating gate conductive layer through said first gate insulating layer in write and erase modes, said programming voltage being in the range from plus 7 volts to 13 volts and said second insulating layer also having a thickness sufficient to provide adequate insulating properties and breakdown voltage resistance; and p0 f) a control electrode formed on said second insulating layer;

[0025] g) and wherein said nonvolatile memory is placed in program mode by applying a voltage drop of from approximately plus 7 volts to 13 volts between said drain diffusion region and said control electrode with said drain diffusion region being more positive relative to said control electrode while maintaining said source diffusion region at ground potential, and wherein said nonvolatile memory is placed in erase mode by applying a voltage drop of from approximately plus 7 volts to 13 volts between said control electrode and said drain diffusion region with said control electrode being more positive than said drain diffusion region while maintaining said source diffusion region at ground potential;

[0026] and wherein said second insulating layer is either not ferroelectric or is ferroelectric but is made of a material having a high dielectric constant which will not change its polarization state when either said program mode or erase mode voltage drops are applied, and wherein said second insulating layer has a dielectric constant which is sufficiently high and a thickness which is chosen so as to raise the capacitance of the parallel plate capacitor defined by said control electrode, said second insulating layer and said floating gate conductive layer relative to the capacitance of the parallel plate capacitor defined by said floating gate conductive layer, said first gate insulating layer and said first conductive type semiconductor region so as to cause an electric field across said first gate insulating layer which has sufficiently high to cause Fowler-Nordheim tunneling of charges across said first gate insulating layer during both said erase mode and said program mode;

[0027] and wherein said first gate insulating layer is thin enough to permit Fowler-Nordheim tunneling during both said program mode and said erase modes when either said programming or said erase voltage drops are applied.

[0028] The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numer als designate the same elements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a view schematically showing the construction in section of a conventional memory cell 1.

[0030]FIG. 2 is a view schematically showing the construction in section of a memory cell according to an embodiment of the present invention.

[0031]FIG. 3 is a conceptual view showing the construction of an LSI memory for explaining the principle of writing information into memory cells according to an embodiment of the present invention.

[0032]FIG. 4 is a conceptual view showing the construction of an LSI memory for explaining the principle of reading information from memory cells according to an embodiment of the present invention.

[0033]FIG. 5 is a conceptual view showing the construction of an LSI memory for explaining the principle of erasing information stored in memory cells according to an embodiment of the present invention.

[0034]FIGS. 6A through 6D are views showing the manufacturing process of the memory cell 3.

DETAILED DESCRIPTION OF THE INVENTION

[0035]FIG. 2 shows a schematic in section of a memory cell 3 of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

[0036] Referring to FIG. 2, a p-type silicon well 12 comprised of a first conductive type semiconductor region has formed therein an n⁺ drain 8 comprised of a second conductive type diffusion region, and an n⁺ source 10 formed in the same way. The two source and drain regions define a channel region 14 therebetween in the well 12. On top of the well 12 there are laminated a thin silicon dioxide film 2 that is a first gate insulating layer which serves as a gate oxide, a polysilicon layer 32 that is a conductive layer and a high dielectric layer 34 which serves as a second insulating layer. The high dielectric layer 34 is composed of a material having high dielectric constant substantially higher than 21 and not less than 50. The high dielectric layer 34, referred to as the second insulating layer in the claims, can be made not only with high dielectric materials such as SrTiO₃ (strontium titanate) but also by using ferroelectric materials which will not change their polarization state when either the programming mode or erase mode voltages are applied for either writing information to the memory cell 3 or erasing information therefrom. SrTiO₃ is used for the high dielectric layer 34 in this embodiment. Also, a polysilicon layer 36 serving as a control electrode is formed on top of SrTiO₃ layer 34.

[0037] The high dielectric layer has a dielectric constant and thickness chosen so as to raise the capacitance of the parallel plate capacitor defined by the control electrode 36, the second insulating layer 34 and the floating gate conductive layer 32 (hereafter referred to as the first capacitor) relative to the capacitance of the parallel plate capacitor defined by the floating gate conductive layer 32, the first gate insulating layer 2 and the first conductive type semiconductor region 14 (hereafter referred to as the second capacitor). The first capacitor's capacitance must be raised high enough relative to the capacitance of the second capacitor so as to cause an electric field gradient across the first gate insulating layer 12 which is sufficiently high to cause Fowler-Nordheim tunneling of charges across the first gate insulating layer when either the program mode or erase mode voltages are applied. Of course the thickness and dielectric constant of the first gate insulating layer 2 must also be selected to allow this Fowler-Nordheim tunneling to occur in both program and erase modes. Many ferroelectric materials such as PZT can change their polarizations under differing voltage conditions, and these changes in polarization alter their dielectric constants. If the dielectric constant of the second insulating layer 34 changes from one value under program mode voltage conditions and another value under erase mode conditions, the operation of the nonvolatile memory could become erratic or inoperative. Strontium titanate is a good choice for the second dielectric layer 34 because it has a high dielectric constant and it is not ferroelectric above temperatures of 40 degrees Kelvin so its polarization and dielectric constant will not change between erase mode and program mode voltage conditions.

[0038] Information can be written and erased into and from the memory cell 1 constructed as described above by electricity.

[0039] The memory cell 3 constructed as above has two stable states: a first state in which a logic “0” is stored, which is reached by applying the program mode voltage conditions given in FIG. 10, and a second state in which the logic “0” has been erased and a logic “1” has been stored, which is reached by applying the erase mode voltage conditions given in FIG. 10. These two stable states are utilized to implement a nonvolatile memory.

[0040] Operation of writing and erasing information into and from the memory cell 1 will be described below. To enter program mode, i.e., write a logic “0” into the memory cell 3, a voltage of approximately 10 V (preferably between 7 and 13 volts and more preferably between 8 and 12 volts) is applied to the drain 8 of the memory cell 3 relative to the control electrode 36 thereof, typically by applying +5 volts to the drain 8 and −5 volts to the control electrode 36 while holding the source at 0 volts. As a result of application of this write voltage, an electric field develops between the polysilicon layer 32 and the drain 8 which causes some of electrons within the polysilicon layer 32 to tunnel through the silicon dioxide film of first gate insulating layer 2 and enter the drain 8. As described above, the programming write voltage of only 10 volts can effect write operation. That is because the SrTiO₃ layer 32 is comprised of high dielectric substance and thus the voltage drop across the first gate insulating layer 2 relative to the total applied programming write voltage increases. In other word, in spite of the lower programming write voltage, the electric field strength across the first gate insulating layer 2 necessary to cause Fowler-Nordheim tunneling of charges out of the floating gate layer 32 and into the drain 8 can be obtained which is necessary to write a logic 0 into the memory by altering its threshold voltage in a nonvolatile fashion. This means that the memory cell 3 has the logic “0” stored therein. The memory cell 3 with the logic “0” serves as a transistor with a lower threshold voltage.

[0041] Meanwhile, to erase the logic “0” from the memory cell 3 and store the logic “1” therein, some of electrons within the drain 8 need injecting into the polysilicon floating gate layer 32. This is effected by generating an electric field of the opposite polarity to that produced when writing the logic “0”. This is done by entering the erase mode detailed in FIG. 10 by applying a voltage of approximately +10 V (preferably between 7 and 13 volts, more preferably between 8 and 12 volts) to the gate electrode 36 relative to the drain 8 thereof, typically by applying +10 volts to the control electrode 36 while holding the drain 8 and the source 10 at 0 volts. In this stable state in which the logic “0” is erased from the memory cell and the logic “1” is stored therein, the memory cell 3 serves as a transistor with a higher threshold voltage.

[0042] Next, the operation of reading information from the memory cell 3 will be described.

[0043] It is decided whether a logic “0” is stored or a logic “1” is stored in each memory cell by determining whether or not current flows through the channel region 14 when a voltage of some 5 V is applied between the source 10 and the drain 8 of the memory cell 3 and no gate voltage is applied to the gate 36.

[0044] More specifically, Since the memory cell 3 with a logic “0” behaves like a transistor with the lower threshold voltage as described above, and the applied gate voltage of 0 volts exceeds the lower threshold voltage there flows current through the channel region 14. Meanwhile, when a logic “1” is stored in the memory cell, the memory cell behaves like a transistor with the higher threshold voltage as described above, and the applied gate voltage of 0 volts does not exceed the higher threshold voltage. Thus no current flows through the channel region 14.

[0045] Next, an example of an LSI memory constructed using the aforementioned memory cell 3 will be given. First described is the principle of operation involved when information is written.

[0046] A conceptual view of the construction of a 1024-bit memory LSI is shown in FIG. 3.

[0047] A memory cell array A has 32 by 32, i.e. 1024 memory cells (1 K. bits) arranged in matrix form. To the drain 8 of each memory cell 3 is connected the source of row select transistor 7. A row decoder 40 drives word lines WL which are each connected to the control electrode of each memory cell 3. Select control lines SL are each connected to the gate electrode of each row select transistor 7 to assist in writing and erasing data to the array. A column decoder 6 drives column data lines DLs which are each connected to the drain of each row select transistor 7.

[0048] Now the way in which information is written into a memory cell 3_(m,n) will be described with reference to FIG. 3. To write a logic 0 into a memory cell at column m and row n, a programming voltage V_(pp) need applying to only the drain 8 of the memory cell 3_(m,n) relative the control electrode 36 thereof. This is effected by applying the voltage V_(pp) of some 10 volts to only the data line DLm with the decoder 38, applying a voltage V _(dd) to only the Select control line SLn and applying ground voltage equal in potential to the well to all the word lines WL. It is noted that, in this state, the row select transistor 7, which is connected with the Select control line SLn, has a conductive channel formed between the source and the drain. As described above, an electric field develops between the polysilicon layer 32 and the drain 8 of only the memory cell 3 _(m,n) which causes some of electrons within the polysilicon layer 32 to move into the drain 8. This means that the memory cell 3 _(m,n) has the logic “0” written.

[0049] Next, the way in which only the logic “0” stored in the memory cell 3 _(m,n) is erased and changes into a logic “1” will be described with reference to FIG. 4. The construction in shown in FIG. 4 is the same as shown in FIG. 3. To erase only the logic “0” stored in the memory cell 3 _(m,n), an electric field of the opposite polarity to that produced when writing the logic “0” need to develop between the polysilicon layer 32 and the drain 8. This is effected by applying the voltage V_(pp) of some 10 volts to only the word line WLn with the row decoder 40, applying the voltage V _(dd) to only the Select control line SLn and applying ground voltage equal in potential to the well and an inhibit voltage Vi to the data line DLm and the rest of all data line, respectively. It is noted that, in this state, all the row select transistors 7, which are connected with the Select control line SLn, have each a conductive channel formed between the source and the drain. As described above, the electric field develops between the polysilicon layer 32 and the drain 8 of only the memory cell 3 _(m,n) which causes some of electrons within the drain 8 to move into the polysilicon 32.This means that the logic “0” stored in the memory cell 3 _(m,n) has changed into the logic “1”.

[0050] The principle of operation for reading information from the memory cell 3 _(m,n) is described below with reference to FIG. 5. The construction shown in FIG. 5 is the same as shown in FIG. 3. To read data stored in the memory cell 3 _(m,n) the two possible stable states of the memory cell 3 _(m,n) need distinguishing and the resulting information need putting out.

[0051] More specifically, the voltage V _(dd) is applied to only the line SLn of Select control lines SL and the data line DLm has the voltage V _(dd) applied to through a resistor 30. Also, the source 10 of the memory cell 3 _(m,n) is grounded. As a result, there is a potential difference V _(dd) between the source and the drain because the row select transistors 7 _(m,n) , which are connected with the Select control line SLn, have a conductive channel formed between the source and the drain. Further, To the control electrode 36 of the memory cell 3 _(m,n) is applied through the word line WLn a voltage Vm which is halfway between the lower threshold voltage and the higher threshold voltage.

[0052] In this state, when the memory cell 3 _(m,n) has a logic “0” stored therein its channel region 14 is conductive because the voltage Vm exceeds the lower threshold voltage of the memory cell 3 _(m,n). The current flowing through data line DLm is directed to ground via the conductive memory cell 3 _(m,n) As a result, the column decoder 6 has no input of current from the data line DL. Conversely, when the memory cell 3 _(m,n) has a logic “1” therein its channel region 14 is non-conductive because the voltage Vm does not exceed the higher threshold voltage. The current flowing through data line DL_(m) is not conducted to ground through cell 3 _(m,n) and therefore it is injected into the column decoder 6 without loss to ground.

[0053] The column decoder 6 is arranged to put out only the current from the data line DL_(m). This output is amplified and read by the sense amplifier 10. It is noted that the voltage V_(dd)is applied the rest of data lines through the resistor 30 for the case where data are read from the memory cells at same time.

[0054] The manufacturing process for the memory cells 3 having the construction as described above will be described below with reference to FIGS. 6A to 6D.

[0055] With an n-type silicon substrate 22 prepared, a p-type silicon well 12 is created within the silicon substrate 22 and is divided into the plural by field oxide layers 18 (FIG. 6A). A thin silicon dioxide film 2 is formed on top of the p-type silicon well 12 by thermal oxidation (FIG. 6B). It is noted that threshold voltage of the memory cell is arranged by implanting dopant into the well 12. Then after forming a resist pattern 30 on top of a thin silicon dioxide portion 28 in order to create a drain and a source, arsenic or phosphorus is ion-implanted into the well 12 and thermally diffused, thereby forming an n⁺ drain 8 and an n⁺ source 10 within the well 12 (FIG. 6C). Then removing the resist pattern 30, a polysilicon layer 32, a SrTiO₃ layer 34 and a polysilicon layer 36 are deposited in respective order by the CVD method (FIG. 6D). The result is then subjected to etching using resist as a mask thereby forming the polysilicon layer 32, the SrTiO₃ layer 34 and the polysilicon layer 36 (FIG. 2). Thereafter, the wiring between each memory elements is completed and then the memory elements is covered with an insulating layer (not shown).

[0056] As described above, the LSI memory constructed using the memory cells 3 can work as memory without such tunneling by using the thin silicon dioxide portion 2 a as used in the prior art memory cell 1. In alternative embodiment, the thin silicon dioxide portion may be provided in the silicon dioxide film 2.

[0057] Although, in the above embodiment, the SrTiO₃ layer is used as the high dielectric layer 34,in alternative embodiment, layer 34 may also be comprised of other high dielectric substances which stable dielectric constants that will not change polarization when various voltage conditions are applied such as are used in programming, erasing and reading the nonvolatile membory cell 3.

[0058] Also, although, in the above embodiment, the polysilicon layers is used for the conductive layer and the control electrode respectively, in alternative embodiment, layer comprised of other high melting point metal may be used.

[0059] In addition, although the first conductive type has been assumed to be p-type and the second to be n-type in the above embodiment, in alternative embodiment, the first conductive type is n-type and the second is p-type.

[0060] The nonvolatile semiconductor memory according to the present invention is characterized in that layer comprised of high dielectric substance like SrTiO₃ is used as the second insulating layer. Therefore, when a programming voltage is applied between control electrode and ether of diffusion regions the partial pressure applied to the first insulating film relative to the programming voltage increases. In other words, in spite of the lower programming voltage, the electric field strength in the first insulating layer can be obtained which is necessary to write or erase information into or from the memory. Accordingly, the miniaturization and integration of the nonvolatile semiconductor memory can be facilitated.

[0061] Although the present invention has been fully described by way of example with reference to the accompanying drawings, it is to be noted here that various changes and modifications will be apparent to those skilled in the art. Therefore, unless otherwise such changes and modifications depart from the scope of the present invention as defined by the appended claims, they should be construed as included therein. 

What is claimed is:
 1. A device including a nonvolatile memory having write, erase and read modes, comprising: a) a first conductive type semiconductor region; b) a pair of second conductive type diffusion regions formed within said first conductive type semiconductor region forming source and drain diffusion regions separated by a channel region comprised of at least a portion of said first conductive type semiconductor region; c) a first gate insulating layer formed on said first conductive type semiconductor region; d) a floating gate conductive layer formed on said first gate insulating layer; e) a second insulating layer formed on said floating gate conductive layer, said second insulating layer being comprised of a layer of insulating material which has a dielectric constant which is sufficiently high to lower a programming voltage needed to cause Fowler-Nordheim tunneling of charges into or out of said floating gate conductive layer through said first gate insulating layer in write and erase modes, said programming voltage being in the range from plus 7 volts to 13 volts and said second insulating layer also having a thickness sufficient to provide adequate insulating properties and breakdown voltage resistance; and f) a control electrode formed on said second insulating layer; g) and wherein said nonvolatile memory is placed in program mode by applying a voltage drop of from approximately 7 volts to 13 volts between said drain diffusion region and said control electrode with said drain diffusion region being more positive relative to said control electrode while maintaining said source diffusion region at ground potential, and wherein said nonvolatile memory is placed in erase mode by applying a voltage drop of from approximately plus 7 volts to 13 volts between said control electrode and said drain diffusion region with said control electrode being more positive than said drain diffusion region while maintaining said source diffusion region at ground potential; and wherein said second insulating layer is either not ferroelectric or is ferroelectric but is made of a material having a high dielectric constant which will not change its polarization state when either said program mode or erase mode voltage drops are applied, and wherein said second insulating layer has a dielectric constant which is sufficiently high and has a thickness which is chosen so as to raise the capacitance of the parallel plate capacitor defined by said control electrode, said second insulating layer and said floating gate conductive layer relative to the capacitance of the parallel plate capacitor defined by said floating gate conductive layer, said first gate insulating layer and said first conductive type semiconductor region so as to cause an electric field across said first gate insulating layer which has sufficiently high to cause Fowler-Nordheim tunneling of charges across said first gate insulating layer during both said erase mode and said program mode; and wherein said first gate insulating layer is thin enough to permit Fowler- Nordheim tunneling during both said program mode and said erase modes when either said programming or said erase voltage drops are applied.
 2. A device including a nonvolatile memory according to claim 1, wherein said pair of diffusion regions are source and drain regions, so that a conductive channel is selectively formed between said source region and said drain region under predetermined conditions, and wherein charges which have entered into said floating gate conductive layer by Fowler-Nordheim tunneling under predetermined programming voltage conditions are trapped there, and wherein, under other predetermined programming voltage conditions, charges leave from said floating gate conductive layer by Fowler-Nordheim tunneling thereby altering the threshold voltage of said device in accordance with the amount of trapped charge in said floating gate conductive layer such that a conductive channel is selectively formed between said source diffusion region and said drain diffusion region depending upon the state of trapped charges in said floating gate conductive layer.
 3. A device including a nonvolatile memory according to claim 1, wherein strontium 2 titanate (SrTiO₃) is used as said second insulating layer, said strontium titanate having a dielectric constant greater than
 50. 